1. Field of the Invention
The present invention relates to a semiconductor device manufacturing, and more particularly to a self aligned contact pad and a method for forming thereof.
2. Description of the Related Art
Recently, with the advance of semiconductor technique, a trend toward smaller design rules for semiconductor devices such as Gbit scale DRAMs has proceeded to the extend that alignment margin can hardly be secured when aligning a contact plug with a semiconductor layer or interconnect layer underlying the contact plug. Accordingly, for sub-quarter micron semiconductor devices, a manufacturing process is employed which permits the contact plug to be formed by self alignment with a semiconductor layer or interconnect layer underlying the contact plug. U.S. Pat. No. 4,992,848 disclosed self aligned contact process the disclosure of which is incorporated herein by reference.
Advantages of the self aligned contact(hereinafter referred to xe2x80x9cSACxe2x80x9d) are as follows. First, the alignment margin for contact opening formation by photographic process can be increased. Second, the contact resistance can be reduced because all the areas defining the contact opening can be used in contact areas. For these reasons, emphasis has been place upon the SAC technique.
IEDM ""95, p.907 and IEDM ""96, p.597, the disclosures of which are incorporated herein by reference, disclosed SAC process wherein SAC patterns resemble circle type or eclipse type, storage node contact opening and bit line contact opening are formed in the thick insulating layer, separately, i.e., spaced apart from each other.
As is well known, as the device pattern size becomes smaller, i.e., as the aspect ratio of the contact hole becomes high, the area which is to be etched reduces and the depth of the contact hole increases. As a result, during the step of etching the thick insulating layer, etching byproducts cannot easily diffuse out from such deep and narrow openings thereby reducing etching rate. In severe case, etching rate significantly reduces and etching can be ceased, i.e., so called etch stop phenomenon.
To solve the etch stop phenomenon, the etching must be performed under the condition that formation of the byproduct such as polymer is suppressed and the etching time must be increased. However, in case of such etching condition, since etching selectivity between layer to be etched and another stopper becomes poor, the gate capping layer and gate spacer can be also etched during the SAC etching, thereby resulting in an electrical bridge between the SAC pad and gate electrode.
Y.Kohyama et al, has proposed a method for forming SAC pad, wherein the SAC openings for storage node and bit line are merged together, in the article entitled xe2x80x9cA Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyondxe2x80x9d, symp, on VLSI tech, digest of technical papers, pp. 1718, 1997, the disclosure of which is incorporated herein by reference.
In this method, the gate SAC pattern (which indicates resist area) is the same as active area and is shifted by a half pitch to gate direction. Therefore, the photoresist pattern area is so small that the polymer formation is very low during the step of SAC etching. As a result, etching selectivity between the insulating layer and the nitride layer of gate spacer and gate mask layer becomes poor. This is because the polymer formation is proportional to the photoresist pattern area and the etching selectivity ratio increases with polymer formation. Further, the SAC pad has an upper surface size confined within the space between adjacent gate lines. This is because over-etching is generally performed after polysilicon CMP and thereby the top surface of resulting SAC pad is lower in level than that of the gate stack. This results in a narrow process margin of alignment between the SAC pad and later-formed bit line contact. Also, after conventional CMP process for electrical separation, over-etching process is generally conducted on the exposed layer of polysilicon, nitride, and oxide and thereby producing byproducts which must be eliminated by additional cleaning, process.
The present invention is directed toward providing a method for forming a SAC pad in a semiconductor device which can prevent gate capping layer from being etched during SAC etching of an insulating layer and can increase top surface areas of the SAC pad for a wide process window.
A feature of the present invention is the formation of a merged SAC opening which exposes a plurality of contact areas of a semiconductor substrate. The merged SAC opening may expose a storage node contact area and a bit line contact area simultaneously. The SAC is opened by etching the insulating layer selectively with respect to the capping layer of the stacked gate electrode and sidewall spacer. Such merged SAC pattern is advantageously formed in order to increase etching selectivity during SAC etching and provide a large process window.
Another feature of the present invention is performing etching back technique for the purpose of electrical separation of each SAC pads unlike conventional CMP technique. The etching back technique uses a gas chemistry based on fluorine and carbon. More specifically, etching back technique includes first step of etching the SAC composing material down to underlying the insulating layer. First step etching back uses a mixed gas containing SF6, CF4 and CHF3. Second step of etching back is conducted on the conductive material and the insulating layer down to a top surface of the capping layer by using a mixed gas containing SF6, CF4 and CHF3. Third step of etching back is conducted on the capping layer selectively with respect to the conductive material by using a mixed gas containing CF4 and CHF3.
These and other features are provided, according to the present invention, by forming gate electrode layers of a polysilicon and a metal silicide such as tungsten silicide layer on a semiconductor substrate. Gate capping layers of a nitride layer and an oxide layer are deposited on the gate electrode layers. Through photographic process, selected portions of the deposited layers are etched to form spaced apart gate electrode structures. Sidewall spacers are then formed on sidewalls of the gate electrode structures by the process of depositing a material layer and etching back thereof. The material for sidewall spacer comprises a silicon nitride layer.
An insulating layer composed of an oxide is then deposited to completely cover the gate structures, filling spaces between adjacent gate structures. The insulating layer comprises borophosphosilicate glass(BPSG) oxide, undoped silicate glass(USG) oxide and high density plasma(HDP) oxide.
Using a contact pad formation mask, selected portions of the oxide insulating layer are etched selectively with respect to nitride of capping layer and spacer and thereby to form SAC openings to the substrate. Both storage node and bit line contact areas of the substrate are simultaneously exposed by single SAC opening for the purpose of a wide process window.
A conductive material is then deposited in the SAC openings and on the oxide insulating layer. The conductive material is made of a material that has an etching selectivity with respect to nitride. For electrical separation each SAC pad from one another, etching back process is carried out on the conductive material and the insulating layer down to a top surface of the capping layer. At the end of the etching back process, a top portion of the capping layer is selectively etched with respect to the conductive material and SAC pads are formed.
Subsequently, bit line and capacitor are formed to be electrically connected to the corresponding SAC pads through contact plugs formed in selected portions of insulating layer.